In high-speed communication, it is quite common to place the data from one data stream into several slower data streams, for example, for transmission over cables or a backplane to another circuit board. During transmission, the data streams may incur different path delays. As such, a channel-alignment process may be needed to synchronize the different low-speed data streams before they can be recombined into a single high-speed data stream. In the SONET/SDH standard, a frame pulse may be used as an alignment signal, while other packet transmission protocols may rely on other mechanisms, such as a programmable code group, as an alignment signal.
According to one traditional approach, channel alignment is accomplished by designing a dedicated alignment circuit (e.g., implemented using ASIC-type circuitry) for each group of channels to be synchronized. In one exemplary prior-art architecture that supports up to eight different low-speed channels, there are seven alignment circuits: one 8-channel alignment circuit, two 4-channel alignment circuits, and four 2-channel alignment circuits. The seven alignment circuits can support the following different modes of operation:                Synchronize all eight channels using the 8-channel alignment circuit.        Synchronize four channels using one of the 4-channel alignment circuits, while synchronizing the other four channels using the other 4-channel alignment circuit.        Synchronize four channels using one of the 4-channel alignment circuits, synchronize another two channels using one of the 2-channel alignment circuits, and synchronize the remaining two channels using another of the 2-channel alignment circuits.        Use each of the four 2-channel alignment circuits to synchronize a different pair of channels.While this scheme provides an acceptable solution when there are only eight channels to be synchronized, the number of alignment circuits needed to support different alignment modes becomes unacceptably large with increasing numbers of channels. For example, for 32 channels, an analogous channel-alignment scheme would require 36 different channel-alignment circuits: one 32-channel circuit, one 28-channel circuit, one 24-channel circuit, one 20-channel circuit, two 16-channel circuits, two 12-channel circuits, four 8-channel circuits, eight 4-channel circuits, and sixteen 2-channel circuits.        
Another traditional approach is to use programmable logic (e.g., FPGA-type logic) to implement each different alignment circuit for each different operating mode. While this solution provides the flexibility needed to support any desired channel-synchronization configuration, it does so at the cost of increased die area and processing time associated with FPGA-type programmable logic as opposed to smaller, faster ASIC-type circuitry.